CV-X-IF Coprocessor
Sample RISC-V coprocessor implementing a custom BITREV instruction via the CV-X-IF interface.
Sample RISC-V coprocessor implementing the R-type BITREV instruction via the CV-X-IF interface for the cv32e40px core. Includes hardware decode and execute stages and a C usage example. Serves as a template for custom instruction extension development.
HardwareLow-LevelRISC-V
- Technical
- Source code: Lab Github
- Last commit: 2025-02-27
The Embedded Systems Laboratory (ESL) is part of the Institute of Electrical Engineering at EPFL, and focuses on the definition of system-level multi-objective design methods, optimization methodologies and tools for high-performance embedded systems and nano-scale Multi-Processor System-on-Chip (MPSoC) architectures targeting the Internet-of-Things (IoT) Era.
This page was last edited on 2026-03-03.
This page was last edited on 2026-03-03.