PHEE
Posit-enabled X-HEEP RISC-V platform integrating the Coprosit arithmetic coprocessor.
X-HEEP RISC-V SoC extended with the Coprosit posit coprocessor via CV-X-IF, targeting the cv32e40px CPU. Supports configurable posit sizes and quire operations. Provides QuestaSim simulation, PYNQ-Z2 FPGA synthesis, vendor update management, and test commands.
HardwareLow-LevelRISC-V
- Technical
- Source code: Lab Github
- Last commit: 2026-03-09
The Embedded Systems Laboratory (ESL) is part of the Institute of Electrical Engineering at EPFL, and focuses on the definition of system-level multi-objective design methods, optimization methodologies and tools for high-performance embedded systems and nano-scale Multi-Processor System-on-Chip (MPSoC) architectures targeting the Internet-of-Things (IoT) Era.
This page was last edited on 2026-03-03.
This page was last edited on 2026-03-03.