Full-stack simulation framework running unmodified software stacks on real CPUs while modeling hardware accelerators (VTA, JPEG, Protoacc) via RTL simulation or DSim. Supports multi-accelerator setups, DMA and interconnect latency modeling, and epoch-based scheduling. Integrates with the SimBricks modular simulation platform.
This page was last edited on 2026-03-03.
This page was last edited on 2026-03-03.