HEEPstor
Framework for deploying post-training quantized PyTorch models on X-HEEP RISC-V SoCs.
Open-hardware framework for post-training quantization and deployment of PyTorch models on X-HEEP RISC-V SoCs. Provides automated INT8/FP32 hybrid quantization, FPGA synthesis, a configurable systolic array, performance analysis, and debugging tools. Targets edge AI workloads.
HardwareInternet of ThingsPyTorchRISC-V
- Technical
- Source code: Lab Github
- Last commit: 2025-02-10
The Embedded Systems Laboratory (ESL) is part of the Institute of Electrical Engineering at EPFL, and focuses on the definition of system-level multi-objective design methods, optimization methodologies and tools for high-performance embedded systems and nano-scale Multi-Processor System-on-Chip (MPSoC) architectures targeting the Internet-of-Things (IoT) Era.
This page was last edited on 2026-03-03.
This page was last edited on 2026-03-03.