Coprosit
Posit and quire arithmetic coprocessor compliant with the RISC-V eXtension interface.
Posit and quire arithmetic coprocessor compliant with the RISC-V CV-X-IF eXtension interface, wrapping the PRAU execution unit. Configurable posit sizes (8–64 bits) and optional operations (log-approximate multiply, divide, sqrt, quire). Integrated into X-HEEP and PHEE; accessible via make configuration flags.
HardwareLow-LevelRISC-V
- Technical
- Source code: Lab Github
- Last commit: 2025-01-31
The Embedded Systems Laboratory (ESL) is part of the Institute of Electrical Engineering at EPFL, and focuses on the definition of system-level multi-objective design methods, optimization methodologies and tools for high-performance embedded systems and nano-scale Multi-Processor System-on-Chip (MPSoC) architectures targeting the Internet-of-Things (IoT) Era.
This page was last edited on 2026-03-03.
This page was last edited on 2026-03-03.