EPFL Combinational Benchmark Suite

Benchmarks for logical gates optimizer

Giovanni De Micheli — Integrated Systems Laboratory

• The EPFL Combinational Benchmark Suite — Published at: IWLS 2015

inactive — entered showcase: 2022-07-05 — entry updated: 2023-03-21

Lab GitHub - last commit: 2022-10-11

This project has not yet been evaluated by the C4DT Factory team. We will be happy to evaluate it upon request.

Simulation

VHDL

MIT